In data acquisition application fields, sometimes multiple analog signals are captured and converted to digital signals over a given time frame simultaneously or parallelly.
In one of the conventional architectures, a sample/hold block is employed for each input channel. All analog signals from the input channels are sampled simultaneously and then enter hold states. During the hold time period, an analog to digital converter (ADC) can be used to convert the sampled analog values to digital signals sequentially until the sampled signals from all the input channels are converted to digital signals. Some drawbacks exist in this architecture. For instance, multiple sample/hold blocks may be required for multiple channels and the sample/hold blocks can be sensitive to high frequency noises without low-pass filtering capabilities.
In another conventional architecture, each input channel employs an individual ADC. Therefore, multiple ADCs are required in a data acquisition system with multiple input channels. Averaging-type ADCs can be used in this architecture to implement synchronization among multiple input channels. However, power consumption, die area and cost of the data acquisition system can be increased if multiple ADCs are employed. In addition, different ADCs may cause mismatch among multiple input channels.